The shift register is used to release the controller outputs. Let's consider the problem of lighting control in the house, there are 20 lamps in the house, each has two states - on/off. If we connect the pins of the chip directly for the lamps, we will need 20 legs. If we decide to add lamps, we will have to replace the chip with a larger number of legs, that is, completely change the device. If we use the shift register, we will only need 3 controller legs, regardless of the number of fixtures, adding fixtures we will add shift registers. So, the necessity and convenience of the device are obvious, let's move on to the logic of work.
Working principle
The shift register is used to convert a linear interface into a parallel one, respectively, it has pins for writing and reading data. Data is sent to the register via two channels - clock and data, state change from a logical zero to a logical unit at the clock input shifts the register by one bit, using the state on data input as a new bit:
| Register status | Data channel status | State after applying "1" to the clock input |
| 01001011 | 1 | 10100101 |
| 01001011 | 0 | 00100101 |
Outputs
The register outputs are denoted by Q1, Q2, ... or QA, QB, ..., each output has a voltage of logical one or zero, displaying the status of the register. For example, if in the register stored number 229 (11100101), then the outputs will have the following states:
| Data | Q 1 | Q 2 | Q 3 | Q 4 | Q 5 | Q 6 | Q 7 | Q 8 |
| 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 |
After shifting by one bit (one on data output):
| Data | Q 1 | Q 2 | Q 3 | Q 4 | Q 5 | Q 6 | Q 7 | Q 8 |
| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 |
Data and clock channel
The operation of the clock channel is switching between zero and one, that is, it does not matter the time that the output is in the state of zero or one. Switching occurs at the moment of voltage change from the logical zero per logical unit. When the clock is triggered, a register shift occurs and the value from the data channel is recorded: if there is a logical zero on the data channel, then a logical zero will be recorded at the time of the clock operation, similarly with the logical unit.
Shift register model
Below is a self-test tool, the CLK button is a clock operation, the switches RST, LC, OE and IN are logical values at the input of the shift register. The outputs Q1 - Q8 are the outputs of the shift register. OUT is the sequential output of data from the register.
